PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 7

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.2.9
13.2.10
13.2.11
13.2.12
13.2.13
13.2.14
13.2.15
13.2.16
13.2.17
13.2.18
13.2.19
13.2.20
13.2.21
28h
13.2.22
2Ch
13.2.23
13.2.24
13.2.25
13.2.26
13.2.27
13.2.28
13.2.29
13.2.30
13.2.31
13.2.32
13.2.33
13.2.34
13.2.35
13.2.36
13.2.37
13.2.38
13.2.39
13.2.40
13.2.41
13.2.42
13.2.43
13.2.44
13.2.45
13.2.46
13.2.47
13.2.48
13.2.49
REGISTER TYPES ...............................................................................................................................59
CONFIGURATION REGISTER...........................................................................................................59
VENDOR ID REGISTER – OFFSET 00h ..................................................................................60
DEVICE ID REGISTER – OFFSET 00h....................................................................................60
COMMAND REGISTER – OFFSET 04h ...................................................................................60
PRIMARY STATUS REGISTER – OFFSET 04h ......................................................................61
REVISION ID REGISTER – OFFSET 08h................................................................................62
CLASS CODE REGISTER – OFFSET 08h ................................................................................62
CACHE LINE REGISTER – OFFSET 0Ch ...............................................................................62
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch.....................................................62
HEADER TYPE REGISTER – OFFSET 0Ch ............................................................................62
PRIMARY BUS NUMBER REGISTER – OFFSET 18h .......................................................62
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................63
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................63
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ...........................................63
I/O BASE ADDRESS REGISTER – OFFSET 1Ch................................................................63
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ..............................................................63
SECONDARY STATUS REGISTER – OFFSET 1Ch............................................................64
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ....................................................64
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h ...................................................65
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h....................65
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ..................65
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ...................................66
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h ..................................66
CAPABILITY POINTER REGISTER – OFFSET 34h ..........................................................66
INTERRUPT LINE REGISTER – OFFSET 3Ch ..................................................................66
INTERRUPT PIN REGISTER – OFFSET 3Ch .....................................................................66
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................67
SUBSYSTEM VENDOR ID REGISTER – OFFSET 40h ......................................................68
SUBSYSTEM ID REGISTER – OFFSET 40h........................................................................68
DIAGNOSTIC/CHIP CONTROL REGISTER – OFFSET 44h .............................................68
ARBITER CONTROL REGISTER – OFFSET 44h ...............................................................70
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h ................................................70
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch ..71
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h ...................................................71
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ..........................................72
P_SERR# STATUS REGISTER – OFFSET 68h....................................................................73
CLKRUN REGISTER – OFFSET 6Ch ...................................................................................74
PORT OPTION REGISTER – OFFSET 74h..........................................................................74
CAPABILITY ID REGISTER – OFFSET 80h .......................................................................76
NEXT ITEM POINTER REGISTER – OFFSET 80h ............................................................76
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h ............................76
POWER MANAGEMENT DATA REGISTER – OFFSET 84h.............................................77
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h ..........................77
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 88h ....................77
CAPABILITY ID REGISTER – OFFSET 90h .......................................................................77
NEXT ITEM POINTER REGISTER – OFFSET 90h ............................................................77
HOT SWAP CAPABILITY STRUCTURE REGISTER – OFFSET 90h ...............................78
HOT SWAP SWITCH REGISTER – OFFSET 94h ...............................................................78
...................................................................................................................................................65
...................................................................................................................................................66
Page 7 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A