PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 61

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.4 PRIMARY STATUS REGISTER – OFFSET 04h
Bit
7
8
9
15:10
Bit
19:16
20
21
22
23
24
26:25
27
28
29
30
31
Function
Wait Cycle
Control
P_SERR#
enable
Fast Back-to-
Back Enable
Reserved
Function
Reserved
Capabilities
List
66MHz
Capable
Reserved
Fast Back-to-
Back Capable
Data Parity
Error Detected
DEVSEL#
timing
Signaled Target
Abort
Received
Target Abort
Received
Master Abort
Signaled
System Error
Detected Parity
Error
Type
RO
RW
RW
RO
Type
RO
RO
RO
RO
RO
RWC
RO
RWC
RWC
RWC
RWC
RWC
Description
Read as 0 to indicate PI7C8140A does not perform address / data stepping.
Reset to 0
0: disable the P_SERR# driver
1: enable the P_SERR# driver
Reset to 0
0: disable bridge’s ability to initiate fast back-to-back transactions on the primary
1: enable bridge’s ability to initiate fast back-to-back transactions on the primary
Reset to 0
Returns 000000 when read
Description
Reset to 0000
Set to 1 to enable support for the capability list (offset 34h is the pointer to the
data structure)
Reset to 1
Set to 1 to indicate the primary may be run at 66MHz operation
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the primary
interface to different targets
Reset to 1
0: No parity error detected on the primary (bridge is the primary bus master)
1: Parity error detected on the primary (bridge is the primary bus master)
Reset to 0
DEVSEL# timing (medium decoding)
01: medium DEVSEL# decoding
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated with target
aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master Abort
Reset to 0
Set to 1 when P_SERR# is asserted
Reset to 0
Set to 1 when address or data parity error is detected on the primary interface
Reset to 0
Page 61 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A