PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 6

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
4
5
6
7
8
9
10
11
12
13
3.4
4.1
4.2
4.3
4.4
5.1
5.2
5.3
5.4
6.1
6.2
7.1
7.2
7.3
10.1
10.2
10.3
11.1
11.2
12.1
12.2
3.4.1
3.4.2
TRANSACTION ORDERING ...................................................................................................................38
ERROR HANDLING ..................................................................................................................................41
5.2.1
5.2.2
5.2.3
5.2.4
PCI BUS ARBITRATION ..........................................................................................................................50
6.2.1
6.2.2
CLOCKS ......................................................................................................................................................51
COMPACT PCI HOT SWAP.....................................................................................................................52
PCI POWER MANAGEMENT .................................................................................................................53
12.2.1
12.2.2
12.2.3
12.2.4
RESET ......................................................................................................................................................53
SUPPORTED COMMANDS..................................................................................................................54
BRIDGE BEHAVIOR.............................................................................................................................56
CONFIGURATION REGISTERS.........................................................................................................59
VGA SUPPORT ....................................................................................................................................37
TRANSACTIONS GOVERNED BY ORDERING RULES.................................................................38
GENERAL ORDERING GUIDELINES...............................................................................................39
ORDERING RULES .............................................................................................................................39
DATA SYNCHRONIZATION .............................................................................................................41
ADDRESS PARITY ERRORS .............................................................................................................41
DATA PARITY ERRORS ....................................................................................................................42
DATA PARITY ERROR REPORTING SUMMARY..........................................................................46
SYSTEM ERROR (SERR#) REPORTING...........................................................................................49
PRIMARY PCI BUS ARBITRATION .................................................................................................50
SECONDARY PCI BUS ARBITRATION ...........................................................................................50
PRIMARY CLOCK INPUTS................................................................................................................51
SECONDARY CLOCK OUTPUTS......................................................................................................52
PCI CLOCKRUN ..................................................................................................................................52
PRIMARY INTERFACE RESET .........................................................................................................53
SECONDARY INTERFACE RESET ...................................................................................................54
CHIP RESET .........................................................................................................................................54
PRIMARY INTERFACE ......................................................................................................................55
SECONDARY INTERFACE ................................................................................................................56
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES........................................................................56
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) .............................................57
VGA MODE ..................................................................................................................................37
VGA SNOOP MODE ....................................................................................................................38
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ...................42
READ TRANSACTIONS .............................................................................................................42
DELAYED WRITE TRANSACTIONS ........................................................................................43
POSTED WRITE TRANSACTIONS ...........................................................................................45
PREEMPTION .............................................................................................................................51
BUS PARKING .............................................................................................................................51
MASTER ABORT .........................................................................................................................57
PARITY AND ERROR REPORTING .........................................................................................57
REPORTING PARITY ERRORS.................................................................................................57
SECONDARY IDSEL MAPPING................................................................................................58
Page 6 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A