PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 25

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.7.1 TYPE 0 ACCESS TO PI7C8140A
2.7.2 TYPE 1 TO TYPE 0 CONVERSION
accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the
transaction is targeted.
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The
configuration space cannot be accessed from the secondary bus. The bridge responds to a Type 0
configuration transaction by asserting P_DEVSEL# when the following conditions are met during the
address phase:
The bridge limits all configuration access to a single DWORD data transfer and returns target-
disconnect with the first data transfer if additional data phases are requested. Because read transactions
to configuration space do not have side effects, all bytes in the requested DWORD are returned,
regardless of the value of the byte enable bits.
Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are
completed immediately, regardless of the state of the data buffers. The bridge ignores all Type 0
transactions initiated on the secondary interface.
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI
bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1
configuration command. Type 1 configuration commands are used when the configuration access is
intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is
generated.
The bridge performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the
primary bus and is intended for a device attached directly to the secondary bus. The bridge must convert
the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type
1 to Type 0 translations are performed only in the downstream direction; that is, the bridge generates a
Type 0 transaction only on the secondary bus, and never on the primary bus.
The bridge responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on
the secondary bus when the following conditions are met during the address phase:
The bus command is a configuration read or configuration write transaction.
Lowest two address bits P_AD[1:0] must be 00b.
Signal P_IDSEL must be asserted.
The lowest two address bits on P_AD[1:0] are 01b.
The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number
register in configuration space.
The bus command on P_CBE[3:0] is a configuration read or configuration write transaction.
When the bridge translates the Type 1 transaction to a Type 0 transaction on the secondary
interface, it performs the following translations to the address:
Sets the lowest two address bits on S_AD[1:0].
Decodes the device number and drives the bit pattern specified in Table 2-6 on S_AD[31:16] for
the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0.
Page 25 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A