PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 16

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2
2.1
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across the bridge, and
transaction termination. The bridge has two 128-byte FIFO’s for buffering of upstream and
downstream transactions. These hold addresses, data, commands, and byte enables that are used for
write transactions. The bridge also has an additional four 128-byte FIFO’s that hold addresses, data,
commands, and byte enables for read transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by the bridge. Table 2-1 lists the
command code and name of each PCI transaction. The Master and Target columns indicate support for
each transaction when the bridge initiates transactions as a master, on the primary (P) and secondary (S)
buses, and when the bridge responds to transactions as a target, on the primary (P) and secondary (S)
buses.
Table 2-1. PCI Transactions
As indicated in Table 2-1, the following PCI commands are not supported by the bridge:
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Pin Number
The bridge never initiates a PCI transaction with a reserved command code and, as a target, the
bridge ignores reserved command codes.
The bridge does not generate interrupt acknowledge transactions. The bridge ignores interrupt
acknowledge transactions as a target.
115
117
119
121
123
125
127
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
P_CLKRUN#
P_AD[31]
P_AD[29]
P_AD[27]
P_AD[25]
P_REQ#
P_CLK
Name
Type
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
TS
TS
TS
TS
TS
TS
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I
Pin Number
116
118
120
122
124
126
128
N
Y
Y
Y
Y
Y
Secondary
Y
N
N
Y
Y
N
N
Y
Y
Y
2-PORT PCI-TO-PCI BRIDGE
P_AD[30]
P_AD[28]
P_AD[26]
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
P_GNT#
P_RST#
March 20, 2007 – Revision 1.01
Name
VDD
VSS
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
PI7C8140A
Type
TS
TS
TS
P
P
I
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