PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 54

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
10.2 SECONDARY INTERFACE RESET
10.3 CHIP RESET
11
The bridge is responsible for driving the secondary bus reset signals, S_RST#. The bridge asserts
S_RST# when any of the following conditions are met:
Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted and does
not de-assert until P_RST# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RST# remains asserted until a
configuration write operation clears the secondary reset bit.
S_RST# pin is asserted. When S_RST# is asserted, the bridge immediately 3-states all the secondary
PCI interface signals associated with the secondary port. The S_RST# in asserting and de-asserting
edges can be asynchronous to P_CLK.
When S_RST# is asserted, all secondary PCI interface control signals, including the secondary grant
outputs, are immediately 3-stated. Signals S1_AD, S1_CBE#[3:0], S_PAR are driven low for the
duration of S_RST# assertion. All posted write and delayed transaction data buffers are reset.
Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S_RST# is asserted by means of the secondary reset bit, the bridge remains accessible during
secondary interface reset and continues to respond to accesses to its configuration space from the
primary interface.
The chip reset bit in the diagnostic control register can be used to reset the bridge and the secondary
bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. S_RST#
is asserted and the secondary reset bit is automatically set. S_RST# remains asserted until a
configuration write operation clears the secondary reset bit and the serial clock mask has been shifted
in. Within 20 PCI clock cycles after completion of the configuration write operation, the bridge’s reset
bit automatically clears and the bridge is ready for configuration.
During reset, the bridge is inaccessible.
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
Page 54 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A