cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 101

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-18.
6.3.1.2
The interrupt status descriptor is located in a fixed position in CX28500’s internal register. CX28500 updates this
descriptor after each transfer of interrupt descriptors from its internal queue to the Interrupt Queue in shared
memory. The Host is required to read this descriptor from CX28500’s registers before it processes any interrupts.
The contents of the interrupt status descriptor are reset on hardware reset or soft chip reset or whenever any field
in the Interrupt Queue Descriptor is modified.
Table 6-19
Table 6-19.
28500-DSH-002-C
2
1
0
31
Bit
Bit
lists the details of the Interrupt Status Descriptor.
Field Name
Field Name
MSTRABT
ILOST
PERR
SACK
Non-DMA Interrupt Descriptors Format (3 of 3)
Interrupt Status Descriptor
NOTE:
Interrupt Status Descriptor Register
Value
Host Access
—
—
—
This internal register is directly accessed by the Host.
R
DMA service request acknowledge. Generated to conclude successfully a service request command of
Host service.
0: No PCI parity errors have been detected.
1: PCI Bus Parity Error. Generated when CX28500 detects a parity error on data being transferred into/
from CX28500, either from another PCI agent that writes into CX28500 registers or from CX28500 that
reads data from shared memory. This error is specific to the data phase of a PCI transfer while CX28500
is receiving data. PCI system error signal, SERR*, is ignored by CX28500. To mask the PERR interrupt—
in CX28500's PCI Configuration Space, Function 0, Register 1—Parity Error Response field must be set
to 0.
0: No interrupts have been lost.
1: Interrupt Lost. Generated when CX28500’s (internal) interrupt queue is full and more interrupt
conditions are detected. As CX28500 has no way to store the newest interrupt descriptors, it discards the
new interrupts and overwrites this bit in the last interrupt in an internal queue prior to that interrupt being
transferred out to shared memory. The integrity of the descriptor being overwritten is maintained
completely.
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Value
—
When CX28500 encounters a PCI abort while operating as a PCI master, it does
not attempt to recover from this error. In this case CX28500 asserts the SERR*
signal, and the MSTRABT bit and waits for the Host to reset (i.e., PCI reset or Soft
reset).
This bit is asserted when the target does not assert DEVSEL within a specific PCLK
cycles or when the target terminates a transaction in which CX28500 is the master,
with an abort (i.e., assertion of STOP# with a deassertion of DEVSEL) sequence.
®
Description
Description
Memory Organization
86