cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 116

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.7.2
The Transmit Channel Configuration register contains configuration bits applying to the logical channels within
CX28500. There are 1024 such registers, one for each channel. The TSLP Channel Configuration Descriptor
configures aspects of the channel common to all messages passing through the channel. One descriptor exists for
each logical channel direction.
descriptor.
Table 6-31.
6.7.3
The Buffer Allocation register configures the internal receive memory. There is one TDMA Buffer Allocation register
for each logical channel (i.e., 1024 channel).
channel. The allocation granularity is two dword. For each active channel it is required to specify the following:
•
•
•
28500-DSH-002-C
CX28500’s internal Tx memory is a 32-KB dual RAM, which can be split into 1024 parts, one part for each
31:30
29
28:21
20:3
2
1
0
Bit
The starting location of internal data buffer
The ending location of internal buffer
A threshold. This value is triggered when a request from DMA must be generated to the internal PCI arbiter. As
soon as the channel’s internal FIFO contains less data bytes than the threshold, an attempt to read data from
shared memory is made. The threshold indicates and determines when the TxDMA begins transfer of data to
the TxSLP. Hence, it indicates when a new transmission of a new message can start. If the buffer contains less
TPROTOCOL[1:0]
Field Name
TMASK[7:0]
TSLP Channel Configuration Register
BUFFIEN
EOMIEN
RSVD
PADJ
TINV
TSLP Channel Configuration Register
TDMA Buffer Allocation Register
Value
Table 6-31
—
0
1
2
3
0
1
0
0
1
0
1
0
1
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TRANSPARENT.
HDLC with no FCS.
Used in ISLP or full packet forwarding and/or channel monitoring application.
For this mode, the SHT message detection is disabled. Any number of bytes can be transmitted and
received within any single message including messages of only one byte.
HDLC with FCS16 (FCS–2 bytes).
HDLC with FCS32 (FCS–4 bytes).
Data Inversion disabled.
Data Inversion enabled. Message is transferred to the SIU with polarity change (the inversion is done
to all bits passed).
An 8-bit data mask. Each bit with the value of 1 should contain data when the relevant time slot is
transmitted (e.g., Mask = 10000001, message data is transmitted only on bits 0 and 7, the other bits
are discarded by the receiver).
Reserved.
Pad Count Adjustment disabled. No adjustment is made to the number of pad fill bytes if Zero
Insertions is detected.
Pad Count Adjustment enabled.
Underrun Interrupt disabled.
Underrun Interrupt enabled.
EOM Interrupt disabled.
EOM Interrupt enabled. Interrupt generated upon End Of Message detection when transferring data
from the TSLP to the TSIU.
lists the values and descriptions of each channel configuration
®
Description
Memory Organization
101