cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 24

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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This application uses 30 of the available 32 serial ports. For PCI bus operation, the central Host processor
examines the packet’s sequence and number, and manipulates the table header in local RAM to perform HDLC
packet formatting and de-formatting.
1.6.2
This application illustrates a connection between CX28500 and CX28344 T3/E3 Framer specifying an 6 DS3 serial
ports application for an unchannelized DS3
High-End Router.
Feature List:
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28500-DSH-002-C
30 ports
PCI bus that operates to redirect packets from and to local RAM via a PCI bridge
EBUS that provides a path of control and performance monitoring for local devices
Two TSBUS ports that provide the path for 28 DS1 payload data and 28 DS1 overhead data as a mixed
combination of asynchronous paths
Simultaneous connection of CX28500’s serial port modes, including channelized TSBUS mode and T1/E1,
either channelized or unchannelized
Variable speed per port and channel
Configurable allocation of the time slots
Sufficient bandwidth to perform 28 DS1 paths and 1 DS3 path simultaneously
Low cost and powerful line card interface
High level chip integration
High performance HDLC controller
Supports full-rate DS3 byte streams with T3/E3 overhead and payload
Supports a byte stream of 32 dwords burst size that travels over the PCI bus/bridge and is directly accessible
as shared memory for the Host to process
Uses a high-speed port priority scheme.
connected at the lower port numbers and the Terminal Data Link (TDL) overhead data paths are connected to
the low priority ports.
Uses framers that can be optimally configured through an optional microprocessor. This path can be used as a
inter-processor communication (IPC) path for control and performance monitoring.
Supports concurrent paths of payload and overhead. (The first six ports run simultaneously at 44.2 Mbps, the
others run simultaneously at the TDL rate (192 Kbps).
NOTE:
T3/E3 Frame Relay Switch
For the detailed description of the application’s device connections, see
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Figure 1-3
illustrates how the first payload data path ports are
®
Appendix
C.
Introduction
9