cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 120

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.7.6.1
1. If both pointers point to the same location, this port should be configured to operate in unchannelized mode.
2. If there are two, three, or four time slots, the PORTTYP field in TSIU Port Configuration register must be set to
3. If there are more than four time slots, the PORTTYP field in RSIU Port Configuration register must be set to
4. If serial port is configured to channelized TSBUS mode, RSIU Time Slot Pointer Allocation Descriptor is
In the case of unchannelized mode (i.e., the PORTTYP field in TSIU Port Configuration register is programmed to
0), CX28500 assumes that only one entry (the one pointed to by STARTAD) is used for this port. This frees the
ENDAD pointer to point to any location in the TSIU time slot memory. The differences in these pointers now define
the number of time slots to count for polling purposes as described in section Descriptor Polling.
Table 6-35.
6.7.7
There is one TSIU Port Configuration register per port (see
generates and synchronizes the transmit bit streams associated with the port. There are 32 such registers, one for
each port.
Table 6-36.
28500-DSH-002-C
31:28
27:16
15:12
11:0
31:14
13
12
GENERAL NOTE:
Bit
Bit
This is done by setting the PROTTYP field in TSIU Port Configuration register to 0.
2, 3, or 4, respectively.
either 5, if it is not T1 framing, or 1 if it is.
configured to support more than eight time slots and the TPROT_TYPE bit field in RSIU Port Configuration
register must be set to channelized TSBUS mode.
Field Name
TSTARTAD_TS[11:0]
TXENBL
TENDAD_TS[11:0]
ENDAD must be ≥ STARTAD (meaning, no wraparound).
RSVD
RSVD
TSIU Time Slot Pointers Register
TSIU Port Configuration Register (1 of 3)
Field Name
RSVD
RSVD
Time Slot Allocation Rules
TSIU Port Configuration Register
(1)
Value
0
0
1
0
Value
Reserved.
Transmit Port Disabled. Logically resets the time slot, regardless of TTS_ENABLE bit field in TSIU Time
Slot Configuration Descriptor. This does not affect the bit values in any time slot descriptor.
Transmit Port Enabled. This bit field acts as a logical AND between TTS_ENABLE bit field in TSIU Time
Slot Configuration Descriptor and time slot.
Logically, if TTS_ENABLE bit field in TSIU Time Slot Configuration Descriptor is enabled, it allows all
channels with time slot enable bits set to start processing data. This does not affect the bit values in any
time slot descriptor.
Reserved.
—
—
0
0
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Reserved.
Ending location in the Transmit Time Slot Map of the last time slot assigned to this port.
Reserved.
Starting location in the Transmit Time Slot Map of the first time slot assigned to this port.
Table
6.7.7). This register defines how CX28500
®
Description
Description
Memory Organization
105