cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 85

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

CX28500 interfaces with a system Host using a set of data structures located in shared memory. CX28500 also
contains a set of internal registers, which control CX28500, that the Host can configure. This section describes the
various shared memory data structures and the layout of individual registers that are required for the operation of
CX28500.
6.1
CX28500 supports a descriptor-based memory architecture wherein data is continually moved into and out of a
table of data buffers in shared memory for each active channel. This assumes a system topology in which a Host
and CX28500 both have access to shared memory for data control and data flow. The data structures are defined
in a way that the control structures and the data structures may or may not reside in the same physical memory and
may or may not be contiguous. In other words, this data structure is a table of descriptors with pointers to data
buffers. The Host allocates and de-allocates the required memory space as well as the size and number of data
buffers within that space.
6.1.1
During CX28500's PCI initialization, the system controller allocates a dedicated 1 MB-memory range to CX28500.
The memory range allocated to CX28500 must not map to any other physical or shared memory. Instead, the
system configuration manager allocates a logical memory address range and notifies the system or bus controllers
that any access to these ranges must result in a PCI access cycle. CX28500 is assigned these address ranges
through the PCI configuration cycle. Once configured, CX28500 becomes a functional PCI device on the bus.
As the Host accesses CX28500's allocated address ranges, the Host initiates access cycles on the PCI bus. It is up
to individual CX28500 devices on the bus to claim these access cycles. As CX28500's address ranges are
accessed, CX28500 behaves as a PCI slave device while data is being read or written by the Host. CX28500
responds to all access cycles where the upper 12 bits of a PCI address match the upper 12 bits of CX28500’s Base
Address register (see
For CX28500, a 1 MB-memory space is assigned to the CX28500 Base Address register, which is written into the
PCI configuration space Address 10h, register 4 in PCI Configuration registers. Once a base address is assigned,
a register map is used to access individual device resident registers. The 1 MB-memory range assigned to
CX28500 does not restrict CX28500's PCI interface from attempting to access this memory space. However,
CX28500 cannot respond to an access cycle that CX28500 itself initiates as the bus master.
The register map provides the byte offset from the Base Address register where registers reside. The register map
layout is given in
includes registers that are directly accessed by the Host through the PCI, and the second includes the registers
existing in shared memory that are accessed by CX28500 only through the Service Request Mechanism.
Therefore, the same address offsets, or registers, may appear in both register maps memory spaces.
28500-DSH-002-C
Table 6-1, PCI Register
Memory Architecture
Register Map and Shared Memory Access
Table 3-6, Register 4, Address
6.0 Memory Organization
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Map. It should be noted that there are two address spaces. The first one
10h).
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