cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 178

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure 10-13. Transmit and Receive Channelized non T1 (i.e., N x 64) Mode
28500-DSH-002-C
LEGEND:
GENERAL NOTE
1. E1 Mode employs 32 time slots (0–31) with 8 bits per time slot (0–7) and 256 bits per frame and one frame
2. 2xE1 Mode employs 64 time slots (0–63) with 8 bits per time slot (0–7) and 512 bits per frame and one frame
3. 4xE1 Mode employs 128 time slots (0–127) with 8 bits per time slot (0–7) and 1024 bits per frame and one
4. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
5. CX28500 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock
6. Relationships between the various configurations of active edges for the synchronization signal and the data
7. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled in on the specified clock edge (e.g. RCLK,
8. In configuration (a), synchronization and data signals are sampled/latched on a rising clock edge.
9. In configuration (b), synchronization signal is sampled on a rising clock edge and the data signal is
10. In configuration (c), synchronization signal is sampled on a falling clock edge and the data signal is
11. In configuration (d), synchronization and data signals are sampled/latched on a falling clock edge.
TCLK). All transmit data signals (TDAT) are latched on the specified clock edge.
every 125 µs (2.048 MHz).
every 125 µs (4.096 MHz).
frame every 125 µs (8.192 MHz).
edge independently of any other signal sampling configuration.
signal are shown using a common clock signal for receive and transmit operations. Note the relationship
between the frame bit (within RDAT, TDAT) and the frame synchronization signal (e.g. RSYNC, TSYNC).
sampled/latched on a falling clock edge.
sampled/latched on a rising clock edge.
RSYNC-FALL( d)
RSYNC-RISE(a)
RSYNC-RISE(b)
RSYNC-FALL(c)
TSYNC-FALL(d)
RDAT A-RISE(a)
TSYNC-RISE(a)
TSYNC-RISE(b)
TSYNC-FALL(c)
RDAT A-RISE(c)
TDATA -FALL(b)
TDATA -FALL(d)
RDAT -FALL(b)
RDAT -FALL(d)
TDAT-R ISE(a)
TDAT- RISE(c)
M = Nx8 bits, where M = number of time slots.
:
RCLK
TCLK
M-2
M-2
M-2
M-2
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M-2
M-2
M-2
M-2
M-1
M-1
M-1
M-1
M-1
M-1
M-1
M-1
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0
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1
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Electrical and Mechanical Specification
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