cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 110

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-25.
6.6.5
6.6.5.1
The receive time slot map consists of 4096 time slot descriptors. The entire receive map contains configuration
information for 4096 separate time slots. The CX28500’s serial ports support 4096 time slots, which can be
configured among the CX28500’s 32 receive serial ports by setting the RSIU Time Slot Pointer Assignment.
Numerous mappings of time slots are possible, multiple time slots can be mapped to a single channel; however
each time slot can map to only one channel at a time. For each serial port two time slot maps are required, one for
transmit functions and one for receive functions. The two separate maps are configured independently for transmit
(TSIU Time Slot Configuration Descriptor and TSIU Time Slot Pointer Assignment) and receive direction (RSIU
Time Slot Configuration Descriptor and RSIU Time Slot Pointer Assignment).
6.6.5.2
For each time slot there is an RSIU Time Slot Configuration Descriptor.
There are 4096 entries in memory that set the translation between time slots and logical channels for each of
CX28500's 32 ports. The actual mapping of these time slot descriptors to the 32 ports is done by 32 sets of pointer
pairs (receive and transmit), one pair set for each port, which indicates the start and the end address of the
memory location that belongs to the configured port. Time Slot pointer allocation is described in RSIU Time Slot
Pointer Allocation.
The bit fields of RSIU Time Slot Configuration Descriptor include information:
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28500-DSH-002-C
13
12:0
FOOTNOTE:
(1)
Bit
The normal mode of operation of the CX28500 is to overwrite the Rx Buffer Descriptor with Rx Buffer Status Descriptor. This bit is used
to inhibit this behavior, so that when it is set, the Rx Buffer Descriptor is not overwritten and the Host must rely on interrupts to find out
when the CX28500 relinquishes ownership of the buffers.
Time slot is enabled or disabled
Time slot is a full DS0, or subchanneling enabled so that only a part of 64 Kbps transports information
Indicates if it is the first time slot assigned to the logical channel
Logical channel number
RDMA_ TRSHOLD[12:0]
RDMA Channel Configuration Register (2 of 2)
Field Name
RSIU Time Slot Configuration Register
Time Slot Map
RSIU Time Slot Configuration Descriptor
EOMIEN
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Value
—
0
1
EOM Interrupt disabled.
EOM Interrupt enabled. Interrupt generated when End Of Message detected and no error
occurred (such as too-long message, FCS error, and message alignment error or abort
condition).
Threshold value. As soon as the channel’s internal FIFO contains more than or equal
number of data dwords than the threshold, a request to the RDMA to serve this channel is
generated. The value programmed into this field must not exceed the channel’s buffer size,
and the threshold must not equal 0.
®
Description
Memory Organization
95