cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 95

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.2.3
Any write of any value to a Soft Chip Reset (SCR) generates a soft reset for CX28500. An SCR write affects
CX28500 exactly as PCI Reset, except that the PCI block is not reset. No PCI configuration is performed after a
SCR.
6.2.4
While addressing CX28500 in slave mode, every PCI access must have all four byte enables active. Any PCI
accesses without all four bytes enabled is treated as if all four byte enables were inactive.
6.3
CX28500 generates interrupts for a variety of reasons. Interrupts are events or errors detected by CX28500 during
internal processing. Interrupts are generated by CX28500 and forwarded to the Host for servicing.
CX28500 gathers the many events and errors (generated by all units such as RxDMA and TxDMA, RSLP and
TSLP, and SIU) and notifies the Host by asserting PCI interrupts. Interrupt descriptors are generated by CX28500
and forwarded to the Host for servicing. Individual types of interrupts can be masked from being generated by
setting the appropriate interrupt mask or interrupt disable bit fields in various descriptors. The interrupt mechanism,
each individual interrupt, and interrupt controlling mechanisms are discussed in this section.
6.3.1
CX28500 employs a single Interrupt Queue Descriptor to communicate interrupt information to the Host. This
descriptor is stored within CX28500 in an internal register. The descriptor in this register stores the location and the
size of an interrupt queue in allocated shared memory where the interrupt descriptors is directly pushed by
CX28500 while acting as a PCI bus master. CX28500 requires this information to transfer interrupt descriptors to
shared memory. All the interrupts are processed by the Host, in an Interrupt Service Routine (ISR). CX28500
directly writes Interrupt Descriptors into the shared memory Interrupt Queue using PCI bus master mode.
CX28500's PCI interface must be configured to allow bus mastering.
The Interrupt Queue Descriptor (i.e., Interrupt Queue Pointer and Interrupt Queue Length) is initialized by the Host
via a direct PCI write transaction. After a PCI Reset or Software Chip Reset (SCR), the Interrupt Queue Pointer is
the first register that needs to be initialized. A typical initialization procedure is as follows:
1. The Host writes in the Interrupt Queue Pointer register allocated by performing a direct write to the address of
2. The Host writes the Interrupt Queue Length register by performing a direct write to this location, the value of
Tables 6-14
28500-DSH-002-C
the Interrupt Queue in shared memory.
the interrupt queue length allocated in shared memory.
through
NOTE:
Soft Chip Reset Register
General PCI Note
Interrupt Level Descriptors
Interrupt Queue Descriptor
6-16
list the details of the Interrupt Queue descriptor.
The user can change, at any time, the length of the Interrupt Queue (IQLEN field in the
Interrupt Queue Length register) or the pointer value of the Interrupt Queue Pointer (IQPTR
field in the Interrupt Queue Pointer register). However, writing to these registers while the
chip is operating may result in flushing the interrupts held in the internal FIFO.
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Memory Organization
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