cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 199

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure B-3
followed by a burst read of 6 dwords. The fast back-to-back is disabled. It can be observed that the first cycle takes
5 PCLK cycles (with one PCLK post-data phase) and the second cycle of transferring 6 dwords requires 6 PCLK
cycles.
Figure B-3.
28500-DSH-002-C
GENERAL NOTE:
1. BEx means Byte Enable, where x is a numerical value between 1 and 8. For example, BE1 means byte one is enabled.
C/BE#[3:0]
C/BE#[7:4]
DEVSEL#
AD[63:32]
FRAME#
illustrates how CX28500 operates at 64-bit address-data and performs a burst read of 4 dwords
REQ64#
AD[31:0]
ACK64#
TRDY#
PAR64
IRDY#
PAR
CLK
PCI Burst Read: Two 64-bit Transactions
Bus Cmd
Address
Back Transactions
Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-
BE1
BE2
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Data1
Data2
Data3
Data4
BE3
BE4
Bus Cmd
Address
®
BE1
BE2
Data1
Data2
Data3
Data4
BE3
BE4
Data5
Data6
BE5
BE6
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