cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 91

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.2.1.2.1
Table 6-6
Table 6-6.
Table 6-7
Table 6-7.
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
GENERAL NOTE:
1. In general, reserved fields should be written with zeros.
Dword Number
Number
dword 0
dword 1
dword 2
Dword
All reserved bits must be written to 0 for forward compatibility.
Bits [1:0] must be equal to zero for dword alignment.
dword 0
dword 1
dword 2
dword 3
presents the structure of DCD.
describes these fields.
OPCODE
SACKIEN
Reserved
Length
Shared Memory Pointer
Indirect Register Map
Address
Device Configuration Descriptor
Device Configuration Field Descriptions
Descriptor Field
Device Configuration Descriptor (DCD)
Reserved [31:19]
OPCODE[31:27]
Bit 31
Mindspeed Proprietary and Confidential
Mindspeed Technologies
(bits)
Size
(1)
12
14
32
19
5
1
Value
—
—
—
1
2
0
1
0
Shared Memory Pointer [31:2]
SACKIEN[26]
CONFIG_WR
CONFIG_RD
SACK interrupt disabled
SACK interrupt enabled. An appropriate interrupt is generated after the
command execution is completed.
A read from this field returns all zeros. A write to this field does nothing.
Number of dword memory commands. Zero length equals 16 K, but valid
maximal length is [16 K–1]. Therefore, a length of 0 is invalid; do not use.
Address in shared memory where the Host service request descriptor table
exists. The two LSBs must equal 0 for dword alignment.
Register Map Address to the specified register that needs to be configured.
This address is a dword-aligned address, meaning the 2 LSB must equal to
0. Bits [18:2] contain the map address while bits [31:19] are reserved.
Reserved
Indirect Register Map Address [18:2]
®
(1)
Reserved[25:14]
(2)
Description
(1)
Memory Organization
(2)
Length[13:0]
Bit 0
76