cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 105

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-20.
28500-DSH-002-C
12
11
10
9:1
0
Bit
TARGET_FBTB
Field Name
INTTRS[8:0]
TARGET_64
PCI_EN
Global Configuration Descriptor (2 of 2)
BR
Value
—
—
—
—
—
1
ECCMODE: CX28500 supports a 64-bit wide ECC memory as the shared memory. The special behavior
includes the following:
0: Target (any target that CX28500 can access over the PCI) is not guaranteed to allow 64-bit transfers
when CX28500 is the master. In this case, a single 64-bit transaction is executed in two 32-bit accesses
even when operating in 64-bit PCI (for any transaction greater than a 64-bit transfer, CX28500 always
attempts to transfer 64 bits regardless of the setting of this bit).
1: Target (any target that CX28500 can access over the PCI) is guaranteed to allow 64-bit transfer. In
this case CX28500 always transfers 64 bits whenever possible.
0: Use the fast back-to-back feature as configured in the PCI configuration settings.
1: CX28500 as PCI master attempts to fast back-to-back the PCI transaction to other targets regardless
of PCI configuration settings.
This bit is defined to force CX28500’s fast back-to-back capability regardless of the PCI configuration.
The PCI specification states that if there is a single device in the system that does not support a fast
back-to-back transaction as a target, the fast back-to-back mode is disabled. Setting this bit to 1
instructs CX28500 to ignore the PCI configuration settings and execute fast back-to-back transactions
when appropriate.
The Host can set this bit only if CX28500 is always accessing the same target which is capable of fast
back to back transactions. This is not a violation of the PCI specification, rather it is an implementation
of allowed behavior.
0: Little-Endian Storage Convention (Intel-style). The least significant byte to be stored in and retrieved
from the lowest memory address.
1: Big-Endian Storage Convention (Motorola-style).
An example of little-big Endian byte ordering is shown in Appendix E.
Threshold of internal interrupt queue Service request.
This bit field contains the configuration parameter of DMA internal interrupt service request queue.
Once the internal queue contains at least one interrupt vector, a low priority DMA request is generated
toward the internal PCI arbiter. This request is removed when the internal queue is empty. If the internal
queue contains greater than or equal INTTRS number of descriptors, a high priority request is
generated toward the internal PCI arbiter. This request is removed when the internal queue contains
less than INTTRS descriptors. See the description in DMA Internal Arbiter. This field must never equal
0.
0: PCI Interrupt disabled–global interrupt mask.
1: PCI Interrupt enabled.
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2.
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When updating Buffer Descriptors in the shared memory, the whole Buffer Descriptor is
written (i.e., 64 bits) rather than the status dword only.
When transferring incoming data to shared memory, any transfer which does not include the
end of message is ended in 64-bit alignment.
Since this mode makes sense only if the data buffers are 64-bit aligned, CX28500 assumes
that the three least significant bits in the data pointers of all (i.e., Tx and Rx) buffer
descriptors are 0 regardless of their actual value. CX28500 preserves the actual value when
updating the buffer descriptor with the status. Start of receive message indication—informs
host via SOM-bit in the Receive Buffer Status Descriptor (bit 2 of second dword) that this
data buffer contains the beginning of a message.
®
Description
Memory Organization
90