cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 134

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

7.1
7.1.1
There is one level of reset:
1. Hard PCI Reset
2. Soft Chip Reset
There are two ways to assert a reset:
1. Assert the PCI reset signal pin, PRST*.
2. Assert a service request through the Host interface to perform the soft chip reset.
After reset, the Host needs to configure CX28500 for it to operate. This configuration includes several stages that
should be performed in the following order:
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•
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7.1.1.1
The PCI reset is the most thorough level of reset in CX28500. All subsystems enter into their initial states, including
the PCI interface. PCI reset is accomplished by asserting the PCI signal, PRST*.
The PRST* signal is an asynchronous signal on the PCI bus. The reset signal can be activated in several ways.
The system must always assert the reset signal on power-up. Also, a Host bus to PCI bus bridging device should
provide a way for software to assert the reset signal. Additionally, software-controlled circuitry can be included in
the system design to specifically assert the reset signal on demand.
Asserting PRST* towards CX28500 guarantees that data transfer operations and PCI device operations do not
commence until after CX28500 has been properly initialized for operation. Upon entering PCI reset state, CX28500
outputs a three-stated signal on all output pins and halts activity on all subsystems including the Host interface,
serial interface, and expansion bus.
28500-DSH-002-C
PCI Configuration—needs to be performed only after Hard PCI Reset
Interrupt Queue Configuration
Global Configuration
Channels and Ports Configuration
NOTE:
Initialization
Reset
Hard PCI Reset
The Interrupt Queue needs to be configured before other registers. If the Interrupt Queue is
not configured with the correct value of Shared Memory Interrupt Queue Pointer and
Interrupt Queue Length, it may result in writes to location 0, since the Service Request
Acknowledge (SACK) is written to a zero-address location.
7.0 Functional Description
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