cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 61

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

At reset, CX28500 sets the bits in this register to 0, meaning CX28500 is logically disconnected from the PCI bus
for all cycle types except configuration read and configuration write cycles.
Table 3-3.
28500-DSH-002-C
Field
26:25
20:16
Bit
31
30
29
28
27
24
23
22
21
Register 1, Address 04h (1 of 2)
Name
Status
Reset
Value
01b
1b
1b
0
0
0
0
0
0
0
0
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Type
RR
RR
RR
RR
RO
RO
RR
RO
RO
RO
RO
Detected Parity Error. This bit is set by CX28500 whenever it detects a parity error, even
if parity error response is disabled.
Detected System Error. This bit is set by CX28500 whenever it asserts SERR*.
Received Master Abort. This bit is set by CX28500 whenever a CX28500-initiated cycle
is terminated with master-abort.
Received Target Abort. CX28500 sets this bit when a CX28500-initiated cycle is
terminated by a target-abort.
Unused.
DEVSEL Timing. Indicates CX28500 is a medium-speed PCI device. This means the
longest time it will take CX28500 to return DEVSEL* when it is a target is 3 clocks.
Data Parity Detected. CX28500 sets this bit when three conditions are met:
Fast Back-to-Back Capable. Read Only. Indicates that when CX28500 is a target, it is
capable of accepting fast back-to-back transactions when the transactions are not to the
same agent.
Unused.
66 MHz Capable. Read Only. Indicates the PCI interface is capable of operating at 66
MHz rate.
Unused.
1.
2.
3.
CX28500 asserted PERR* or observed PERR*.
CX28500 was the master for that transaction.
Parity Error Response bit is set.
®
Description
Host Interface
46