cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 186

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

L
If Endurable Latency of a channel is less than Maximum Feasible PCI Latency in both the receive and transmit
directions, no overflow or underflow occurs.
A.10
PCI bus utilization is defined to be the ratio of the amount of time CX28500 uses the bus to the total amount of time
that could be utilized by all components on the bus, including the Host. Utilization is calculated by comparing the
time required to transfer one bit of receive and one bit of transmit information across the PCI and the time required
to fill one bit of internal buffer space.
The time required per bit to transfer across the PCI (Y
the amount of time required for one packet’s transactions by the number of bits in the packet. Giving the average
time to transfer one bit:
Where P is packet length, measured in bits. Hence Y
Z is the amount of data transferred in 32 PCI cycles. ROUNDUP is a simple rounding up function. P is packet
length in bits. PCI Mode is the number of bits transferred by one PCI clock and THR is the FIFO threshold for that
channel.
Similarly for the transmit direction:
Where P is packet length, in bits. Hence Y
Z is the amount of data transferred in 32 PCI cycles. ROUNDUP is a simple rounding up function. P is packet
length in bits. PCI Mode is the number of bits transferred by one PCI clock, and THR is the FIFO threshold for that
channel.
So the utilization, U, of the PCI bus due to one CX28500 is:
28500-DSH-002-C
ch-tx
=
----- -
f
1
ch
* Thr
tx
PCI Bus Utilization
---------------- - 3
P f
---------------- - 3
P f
•
U
•
1
1
pci
pci
=
⎧
⎨
⎩
NumCh
⎧
⎨
⎩
∑
+
+
w
Time for a bit of RX Data
w
Time for a bit of TX Data
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -
Amount time to transfer one bit of RX and TX in/out of CX28500
+
+
⎛
⎝
⎛
⎝
3
3
+
+
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Mindspeed Technologies
⎛
⎝
⎛
⎝
-------------------------- -
PCI Mode
-------------------------- -
PCI Mode
Amount time to transfer one bit across the PCI
bit-tx
64
64
can be represented by:
⎞
⎠
⎞
⎠
+
+
r
r
⎞
⎠
⎞
⎠
bit-rx
+
+
bit
CX28500 PCI Bus Latency and Utilization Analysis
=
⎛
⎝
⎛
⎝
) is calculated as an average over one packet, by dividing
=
-------------------------- -
PCI Mode
-------------------------- -
PCI Mode
---------------- - Read BD
P f
can be represented by:
---------------- - Read BD
P f
•
1
•
P
P
1
pci
pci
{
{
⎞
⎠
⎞
⎠
+
+
®
(
(
3
2
+
+
r
w
+
)
+
)
•
Write Packet Data
•
Read Packet Data
⎛
⎝
ROUNDUP
⎛
⎝
ROUNDUP
(
⎛
⎝
⎛
⎝
----------------------------------------------
MIN TH R Z P
----------------------------------------------
MIN TH R Z P
)
+
(
+
(
Write Status
Write Status
P
(
P
(
, ,
, ,
)
)
)
⎞
⎠
)
⎞
⎠
⎞
⎠
}
}
⎞
⎠
⎫
⎬
⎭
⎫
⎬
⎭
171