cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 173

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure 10-8. EBUS Write/Read Cycle, Motorola-Style
28500-DSH-002-C
GENERAL NOTE:
1. BG* assertion depends on the external bus arbiter. While BG* and BR* are both deasserted, MUSYCC
2. One ECLK cycle after BG* assertion, MUSYCC outputs valid command bus signals: EBE, AS*, R/WR*,
3. Two ECLK cycles after BG* assertion, MUSYCC outputs valid EAD address signals. BGACK* assertion
4. ALAPSE inserts a variable number of ECLK cycles to extend AS* high pulse width and EAD address interval.
5. EAD address remains valid for one ECLK cycle after AS* falling edge. During a write transaction, MUSYCC
6. ELAPSE inserts a variable number of ECLK cycles to extend DS* low pulse width and EAD data interval.
7. EAD write data, EBE, R/WR*, and AS* signals remain valid for one ECLK cycle after BGACK* and DS* are
8. One ECLK after BGACK* deassertion, the BR* output is deasserted and the bus is parked (command bus
9. Command bus is unparked (three-stated) one ECLK after BG* deassertion; two different unpark phases
10. BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus
11. The address line A31 must be asserted in all transactions.
places shared EBUS signals in high impedance (three-state, shown as dashed lines).
and DS*.
occurs three ECLK cycles after BG* and BR* are both asserted.
asserts R/WR* and outputs valid EAD write data one ECLK prior to DS* assertion. During a read transaction,
EAD data lines are inputs.
Read data inputs are sampled on ECLK rising edge coincident with DS* deassertion.
deasserted.
deasserted, EAD three-state). The bus parked state ends when the external bus arbiter deasserts BG*.
are shown, indicating the dependence on BG* deassertion. If BG* remained asserted until the next bus
request, then command bus remains parked until one ECLK cycle following the next BR* assertion.
Caution: Whenever BG* is deasserted, all shared EBUS signals are forced to three-state after one ECLK
cycle, regardless of whether the EBUS transaction was completed. MUSYCC does not reissue or repeat
such an aborted transaction.
request.
R/WR* (write)
R/WR* (read)
See Notes
EAD[31:0]
EBE[3:0]*
BGACK*
ECLK
BG*
BR*
DS*
AS*
1
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Mindspeed Technologies
2
Byte Enables from EBUS Configuration Descriptor
ALAPSE = 0
3
Address
4
(11)
5
ELAPSE = 0
Data
6
®
Electrical and Mechanical Specification
7
8
BLAPSE = 0
9
10
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