cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 182

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

A.1
To check whether CX28500 internal FIFOs can withstand the time delays to their being serviced that are caused by
a combination of PCI latency and other channels requesting service without experiencing an underflow or overflow.
Further to analyze PCI bus utilization.
A.2
A transmitter Underflow (TxBUFF) is defined as the condition that exists when an output FIFO for a specific
channel is emptied before transmission of a complete HDLC frame.
A receiver Overflow (RxBUFF) is caused when CX28500 does not service a channel in time, which in turn is
caused by either excessive PCI bus latency or other channel demands on the PCI. An Overflow is defined as the
condition that exists when the input FIFO for a specific channel is completely full and that channel receives more
input data.
MaxData is the maximum number of data cycles that can be transferred across the PCI bus during one PCI
transaction.
NumCH is the number of channels configured.
A PCI Data Transaction is defined as a PCI transaction that involves a read or write burst of message data to or
from the Host memory. This does not include a read or write burst of a Buffer Descriptor (BD) nor of status bits.
f
f
framing and of storing the status in the SLP (Serial Line Processor) FIFO.
The threshold of a receive channel RSLP FIFO (Thr
the FIFO crosses this level, causes the channel to request service from the DMA (Direct Memory Access)
controller.
The threshold of a transmit channel TSLP FIFO (Thr
in the FIFO crosses this level, causes the channel to request service from the DMA.
The BuffLen (BUFFLEN) of a channel is the internal FIFO length allocated to that channel for use between the SLP
and the DMA.
28500-DSH-002-C
pci
ch
is the internal channel bit rate in bits per second. This value takes into account the overhead caused by HDLC
is the PCI clock rate in Hz.
Objective
Definitions
Appendix A: CX28500 PCI Bus Latency
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Mindspeed Technologies
rx
tx
) is the amount of data in bits that, when the amount of data in
) is the amount of data in bits that, when the amount of data
and Utilization Analysis
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