cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 143

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

The two main channel protocols, HDLC and transparent mode, are described in subsequent sections of this
chapter. HDLC and transparent mode operations perform protocol-specific processing of their respective input and
output serial bit streams and behave differently in their treatment of those bit streams during abnormal conditions.
8.1
From a functional viewpoint, many CX28500 operations are protocol-independent, though some behaviors may
differ between the transmitter and receiver. The protocol-independent operations described below apply to all event
and error handling:
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28500-DSH-002-C
During DMA shared memory, SLP channel protocol and SIU serial port operations, an event or error may occur
that indicates the status of the message transfer process or that affects the outcome of the overall message
transfer process. Unless masked, all such events and errors cause CX28500 to write an Interrupt Descriptor to
the shared memory interrupt queue. Interrupt Descriptors identify the error or event condition, the transmit or
receive direction, and the affected channel or port number.
If CX28500 suspends a channel’s operation, the Host must perform a channel reactivation by issuing either a
Channel Activation Service Request or a Channel Jump Service Request. This is referred to as “requiring
reactivation.” On the receiving side one scenario that would suspend a channel is when a message descriptor
is Host owned and NP = 1 is encountered. On the transmission side, several occurrences of COFA’s will cause
the TSLP to stop transmission, hence suspending all active channels.
If CX28500 deactivates a channel, the Host must perform a channel reactivation by issuing a Channel
Activation Service Request. This is referred to as “requiring complete reactivation.”
The bit fields INHTBSD and INHRBSD in the RDMA/TDMA Channel Configuration registers specify whether
CX28500 writes a Buffer Status Descriptor into the Message Descriptor to indicate that CX28500 has
completed servicing both the message descriptor and its associated data buffer.
During the normal course of shared memory buffer processing, the DMA calculates the position of the next
Message Descriptor within the Message Descriptor Table and reads that Buffer Descriptor to determine
ownership. The Buffer Descriptor’s ONR bit field indicates whether CX28500 or the Host owns that particular
message descriptor and its associated data buffer. CX28500 never writes to a Host-owned descriptor nor
processes its associated data buffer.
Whenever both EOB and EOM events happen together, an EOM interrupt is generated and an EOB interrupt is
not generated for the receive direction. That is, unless the EOM interrupt is disabled (masked) and the EOB
interrupt is enabled (unmasked), in which case an EOB interrupt is generated. This is true even if the cause of
the EOM interrupt was due to an error condition. For the transmit direction, since EOB and EOM are
independent, both interrupts will be reported if they are enabled.
Protocol-Independent Operations
8.0 Basic Operations
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