cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 68

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 4-1.
Table 4-2.
When an EBUS_RD is issued, CX28500 executes a PCI bursted write of EBUS transactions and will store the data
(EAD[31:0]) in an internal buffer. When the EBUS transaction ends, CX28500 bursts the data over the PCI to the
location specified by Shared Memory Pointer (Buffer Address). The EBE[3:0]* drives the programmed EBUS Byte
Enabled (EBE) value set in the Access Control Field dword. If EBE[3:0]* is different from 0000, the Host must
determine which bytes are valid for access.
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
(3)
Number
dword 0
dword 1
dword 2
Dword
Number
dword 0
dword 1
dword 2
dword 3
Dword
All reserved bits must be written with 0’s for forward compatibility.
The two LSB’s must be equal to zero for dword alignment.
The EBUS Base Address Offset is only 31 bits wide. The MSB (bit 31) must be set to 1 for all transactions.
EBUS Base Address
OPCODE[31:27]
Descriptor Field
EBUS Byte Enable
Shared Memory
EBUS Service Request Descriptor
EBUS Service Request Field Descriptions
FIFO_BURST
Reserved
SACKIEN
OPCODE
Pointer
Length
Offset
(EBE)
Bit 31
SACKIEN[26]
(Bits)
Size
14
32
31
5
1
7
1
4
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Value
—
—
—
—
—
6
7
0
0
1
Reserved [25:19]
Shared Memory Pointer[31:2]
EBUS Base Address Offset
EBUS Write command (EBUS_WR)
EBUS Read command (EBUS_RD)
Enable (1) or disable (0) acknowledge via interrupt in the end of the command
execution
Reserved bits should be written with 0s.
Do increment EBUS address (address on the target device) by one after each
EBUS access. This is used to access a continuous segment or block of memory
on the target device that is connected to the EBUS.
Do not increment EBUS address for this access. On some devices, memory
accesses are carried out the writing/reading of one memory location. By setting
FIFO_BURST to one, CX28500 does not increment the EBUS address after an
access. Hence, the address stays the same for the next EBUS access.
The value driven over EBE[3:0]*. Each bit controls a corresponding byte access
on the EBUS. For example, an EBE[3:0] value of 0001 means that Host data
passes to the device attached to the EBUS on byte 0, the least significant byte, of
the EBUS while the other three bytes are inaccessible.
Number of EBUS transactions.
The Shared Memory Pointer (Buffer Address) is a dword–aligned address of the
first buffer to or from which data needs to be transferred from or to the EBUS.
The two LSB’s must be equal to zero for dword alignment.
The EBUS Base Address Offset is the address for the first EBUS transaction. Bit
31 of this dword must be set to 1 in every transaction.
Reserved
FIFO_BURST[18]
(1)
®
(3)
(2)
Description
EBUS Byte Enable
[17:14]
Expansion Bus (EBUS)
Length[13:0]
Bit 0
53