cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 86

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

The only registers that can be directly accessed by the Host as slave reads or writes are the Rx Port Alive, the Tx
Port Alive, the Interrupt Status Descriptor, the Interrupt Queue Pointer, the Interrupt Queue Length, the Service
Request Length, the Service Request Pointer, and the Soft Reset registers specified in CX28500’s Register Map.
When the Host writes directly into a corresponding register, CX28500 behaves as a PCI slave while this write is
performed.
All other registers need to be accessed through the Service Request Mechanism. After the PCI reset, when
CX28500 is ready for configuration, these registers are updated with the appropriate shared memory values
through a Configuration Write Service Request. After the Host has configured the shared memory image of
CX28500’s registers, and CX28500 has finished its local configuration (i.e., SRQ_LEN bit field in Service Request
Length is reset to zero), the Host issues a service request by writing directly into the Service Request Length
register. Writing to this location the actual value of the Service Request Descriptor Table Length from shared
memory causes CX28500 to start performing the Service Request Descriptor Table.
Table 6-1.
Table 6-2.
28500-DSH-002-C
RSLP Channel Status
RSLP Channel Configuration
RDMA Buffer Allocation
RDMA Configuration
RSIU Time Slot Configuration
Base Address
Configuration
Register 4
CX28500
Register
PCI
PCI Register Map
Indirect Register Map Address Accessible via Service Request Mechanism (1 of 2)
Register
FOOTNOTE:
(1)
(2)
(3)
There are two address spaces. The first address space includes registers that are directly accessed by
Host through the PCI. The second address space (shown in
map accessible by CX28500 via the Service Request Mechanism. Therefore, all the registers shown in this
table can be directly accessed by the Host.
During internal initialization, the Service Request Length becomes non-0 to prevent the Host from writing
to this register since the Host can only modify this register when its value is 0. After initialization, this
register is returned to 0, allowing the Host to modify its content.
The Interrupt Status Descriptor is partially readable and partially writable. The write pointer cannot be
modified, but the read pointer is modifiable. Any write accesses to the write pointer are ignored by
CX28500.
Interrupt Status Descriptor
Service Request Pointer
Service Request Length
Interrupt Queue Pointer
Interrupt Queue Length
Transmit Port Alive
Receive Port Alive
Soft Chip Reset
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Register
Address
00000h
01000h
02000h
03000h
04000h
(3)
Number of
Registers
dword
1024
1024
1024
1024
4096
00000h
00004h
00008h
0000Ch
00010h
00014h
00018h
00020h
Offset
Byte
®
Per Time Slot
Number of
Per Channel
Per Channel
Per Channel
Per Channel
instances
Number of
instances
Per Port
Per Port
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Table
6-2) represents the CX28500’s register
Reset Value
Memory Organization
Value
Reset
3FF
—
—
—
—
0
0
0
0
0
0
0
0
(2)
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Write Only
Read Only
Read Only
Read/Write
Read/Write
Access
Write Only
Write Only
Read Only
Type
Access
Type
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