cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 221

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

F.3.2
The following is the list of technical definitions used in this document:
28500-DSH-002-C
Byte
Channel
Channelized
Data Path
Descriptor
Digital Level 1
Signals
Digital Level 2
Signals
DWord
Flag
HDLC Frame
Hyperchannel
Idle Code
Logical Channel Also called a Virtual Serial Port (see VSP, below).
Message
Octet
Pointer
Port
SPE
Structure
SubChannel
Time Slot
Definitions
A group of 8 binary bits. A byte is exactly synonymous with an octet.
A logical bit stream passed through CX28500. The transmit direction is defined as the path
from Host interface to serial port; the receive direction is defined as the path from serial port to
Host interface. The channel rate is configurable.
Refers to a serial port configuration whereby the bit stream is logically partitioned into 8-bit time
slots. Frame synchronization is required and allows mapping of individual bits, time slots, or
Virtual Serial Ports (VSP) into logical channels. This mode is synonymous to PCM Highway.
A data path is one communications channel (i.e., DS1, E1, VT1.5, VT2.0, C-11, C-12,
Unchannelized DS3, or Unchannelized STS-1 signals). One data path occupies a fixed number
of time slots at fixed locations in a Time slot Bus Frame.
A single dword (i.e., 32-bit) control structure that describes some attributes of a data block.
The following Digital Level 1 signals are the channelized data paths transported over the
Payload TSBUS: DS1, E1, VT1.5, VT2.0, C-11, and C-12.
The following Digital Level 2 signals contain the channelized data paths that are extracted and
then transported over the receive Payload TSBUS: DS2, E2, VTG, and TUG-2.
A group of 32 bits. CX28500 assumes that memory is organized as 32-bit words, as viewed
through the PCI interface. This term is equivalent to a dword which is used for historical
reasons to refer to double 16-bit words.
As defined in HDLC, an octet with the value 7Eh.
In the context of an HDLC bit stream, a frame is a packet of information delimited with 7E flags.
This term can be used interchangeably with message or packet. The term frame in this context
is different than a T1 or E1 frame.
Refers to the concatenation of multiple time slots into a single logical channel.
Octet pattern used to fill the time between the closing flag of one message and the opening flag
of the next message. CX28500 supports the following patterns: 7Eh, FFh, and 00h.
Refers to an HDLC frame or packet as delimited by opening and closing 7Eh flags.
Synonymous with byte. Refers to an association of 8 bits.
A single word (i.e., 32-bit) control structure that serves as an address to another word (i.e.,
word-aligned pointer) or byte (i.e., byte-aligned pointer).
One of the 32 full-duplex serial interfaces supported by CX28500.
Synchronous Payload Envelope. This is the envelope used within an STS frame structure to
carry the path layer overhead and payload data in the SONET system.
A general term referring to one or more data structures stored in shared memory.
A portion of a 64 bps time slot. That is, when a time slot is split and utilized as one sub-64 bps
channel, it is referred to as subchannel.
An 8-bit portion of a T1 or E1 frame that repeats every 125 µs, for a total of 64 Kbps.
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