cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 152

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

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Channel Level Recovery Actions:
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8.2.9.2
RSYNC or STB input signal transitions from low to high, but at an unexpected time in comparison to the frame
synchronization flywheel mechanism. COFA errors are only applicable to channelized ports (i.e., unchannelized
ports ignore the RSYNC/STB input). Frame synchronization indicates the expected location of the first bit of time
slot 0 on the receive serial data input. Lacking frame synchronization, the receiver cannot map or align time slots.
This error affects all active channels on the respective port, but does not require a Host recovery action.
Reason:
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Effects:
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28500-DSH-002-C
When the in-progress message reaches the top of the internal FIFO, the entire HDLC message (before the
overflow occurred) is copied to shared memory buffers and their last Receive Buffer Status Descriptors are
written with ONR = HOST, EOM = 1, ERROR = BUFF (if INHRBSD = 0 in
RxERR interrupt is generated, if ERRIEN is set in
overflow.
RDMA is not affected and continues shared memory buffer processing.
If a consecutive overflow condition exists, only the first overflow triggers an overflow interrupt while all
succeeding overflows are discarded and not reported.
If possible, increase internal FIFO size assigned to this channel. For this action, the channel must first be
deactivated.
If necessary, alleviate PCI bus congestion.
Notice that channel reactivation is not required.
Signal failure, glitch, or realignment caused by the physical interface sourcing the RSYNC or STB input signal.
Causes serial interface to enter COFA condition until the RSYNC/STB pulse is followed by at least the
assigned number of time slots for this port, without another unexpected RSYNC/STB pulse.
If a receive message was in-progress, that message is marked as errored. RSLP scans for the opening flag of
the next HDLC message and any subsequent receive messages are discarded until the internal COFA
condition has ended.
When the in-progress message reaches the top of the internal FIFO, the entire HDLC message is copied to
shared memory buffers, and Receive Buffer Status Descriptors are written with ONR = HOST and
ERROR = COFA (if INHRBSD = 0 in
Receive COFA Interrupt is generated (if COFAIEN = 1 in
Note that a TSTB change of alignment causes both a receive and a transmit COFA interrupt, since TSTB
applies to both transmit and receive directions simultaneously.
Normal operations continue after the COFA condition ends.
RDMA is not affected and continues shared memory buffer processing.
NOTE:
Receive Change Of Frame Alignment (COFA)
Since CX28500 completely separates the two processes of storing data in shared memory
buffers and receiving data from the serial interface, it is irrelevant to CX28500 how the
overflow condition was created. To be specific, there is no distinction between a BUFF error
created due to a Host-owned buffer descriptor or due to a latency-induced full FIFO
condition. CX28500 behavior when encountering a buffer descriptor owned by the Host is
described in
the presence or absence of an overflow condition. The effects of an overflow condition,
once detected, are as described above, regardless of the current buffer ownership.
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Table 6-41, Receive Buffer
Section 6.6.4
Section 6.6.4
and
Descriptor. The behavior is the same regardless of
Section
Table 6-28, RSIU Port Configuration
®
6.7.4).
and
Section
Section 6.6.4
6.7.4, indicating a RxBUFF error
and
Basic Operations
Section
Register).
6.7.4).
137