cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 64

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

3.2.1.5
Table 3-6.
3.2.1.6
Table 3-7.
3.2.1.7
Table 3-8.
28500-DSH-002-C
GENERAL NOTE:
1. An active low signal is detected by a trailing asterisk (*).
GENERAL NOTE:
1. An active low signal is detected by a trailing asterisk (*).
Field
31:20
Field
Field
31:24
23:16
19:4
31:0
15:8
Bit
2:1
Bit
Bit
7:0
3
0
Base Address Register
Maximum Latency
Minimum Grant
Interrupt Line
Interrupt Pin
Register 4, Address 10h
Register 5-14, Address 14h–38h
Register 15, Address 3Ch
Reserved
CX28500
Name
Name
Name
Register 4, Address 10h
Register 5–14, Address 14h–38h
Register 15, Address 3Ch
Reset
Value
Reset
Value
Reset
Value
01h
01h
0Fh
0
0
0
0
0
0
0
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Type
Type
Type
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Allows for 1 MB-bounded PCI bus address space to be blocked off as CX28500 space.
CX28500 will respond as a PCI slave with DEVSEL* to all memory cycles whose address
bits 31:20 match the value of bits 31:20 of this register, and those upper address bits are
non-0, and memory space is enabled in the Register 1, COMMAND bit field.
Reads to addresses within this space that are not implemented read back 0; writes have
no effect.
When appended to bits 31:20, these bits specify a 1 MB bound memory range. 1 MB is
the only amount of address space that a CX28500 can be assigned.
CX28500 memory space is not prefetchable.
CX28500 can be located anywhere in 32-bit address space.
This base register is a memory space base register, as opposed to I/O mapped.
Unused.
specified in 0.25 µs increments and assumes a 33 MHz clock. A value of 0Fh means
CX28500 needs to gain access to the PCI bus every 130 PCI clocks, expressed as 3.75
µs in this register.
This value specifies, in 0.25 µs increments, the minimum burst period CX28500 needs.
CX28500 does not have any special MIN_GNT requirements. In general, the more
channels CX28500 has active, the worse the bus latency and the shorter the burst cycle.
Defines which PCI interrupt pin CX28500 uses. 01h means CX28500 uses pin INTA*.
register indicating which Host interrupt controller input is connected to CX28500’s
INTA* pin.
Specifies how quickly CX28500 needs to gain access to the PCI bus. The value is
Communicates interrupt line routing. System initialization software writes a value to this
®
Description
Description
Description
Host Interface
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