cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 54
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cx28500
Manufacturer Part Number
cx28500
Description
Cx28500 Multichannel Synchronous Communications Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28500.pdf
(224 pages)
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2.3
The direct memory access controller (RxDMA and TxDMA) manages all of the memory operations between a
correspondent’s SLP and the Host interface. DMA takes requests from SLP to either fill or flush internal FIFO
buffers, sets up an access to the data buffers in shared memory, and requests access to the PCI bus through the
Host interface.
2.3.1
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Per Channel Configuration
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28500-DSH-002-C
Handles 1024 logical channels.
Supports 32- or 64-bit DMA transactions for 32- or 64-bit PCI bus transactions, respectively.
Configurable Internal Buffer Allocation
Full control of internal buffer size and internal buffer threshold per channel
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Buffer Descriptor Handling
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Autonomous management of Buffer Descriptors
Automatic fetch for next Buffer Descriptor
Automatic Buffer Status Descriptor update and interrupts for End Of Buffer (EOB), Ownership (ONR) and End
Of Message (EOM) conditions
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Complete Buffer Control
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Self-service mechanism
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INHRBD—Status descriptor update/ignore
EOMIEN—Error-free End Of Message (EOM) interrupt enable/disable
ERRIEN Errored EOM enable/disable
ONRIEN—Ownership error
FIFO flushing capability (after soft chip reset, channel activation, and channel deactivation service request)
Separate Buffer Descriptors per channel
LAST bit field set in buffer descriptor indicates the Buffer Descriptor table length (maximum length is 4096
Buffer Descriptors entries)
Automatic fetch of Transmit and Receive Head Pointer Table (THPT and RHPT)
Automatic fetch of Transmit Head pointer Table (THPT) and Receive Head Pointer Table (RHPT) enables
the Buffer Descriptor tables switching without interfering normal operation (channel Jump)
Automatic polling of Buffer Descriptor
Buffer Pointer
Buffer Length
Ownership (Host/CX28500)
End Of Buffer Interrupt Mask (EOBIEN)
Poll/No poll Control
Zero host intervention required
Support self-service for receive to transmit loopback
Automatic Tx Abort Command generation
Direct Memory Access Controller
General Feature List
Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
Internal Architecture
39
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