cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 103

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Descriptor is to be sent to the Host. If the interrupt is not masked, CX28500 generates a descriptor and stores it
internally prior to transferring it to the Interrupt Queue in shared memory.
The internal queue is capable of holding 512 descriptors while CX28500 arbitrates to master the PCI bus and
transfer the descriptors into the Interrupt Queue in shared memory.
As the PCI bus is mastered and after descriptors are transferred out to the shared memory, CX28500 updates the
Interrupt Status Descriptor. When CX28500 updates the WRPTR field in the Interrupt Status Descriptor, it asserts
the PCI INTA# signal line.
If during the transfer of descriptors, the Interrupt Queue in shared memory becomes full, CX28500 stops
transferring descriptors until the Host indicates more descriptors can be written out. CX28500 indicates that it
cannot transfer more descriptors into shared memory by setting the bit field INTFULL in the Interrupt Status
Descriptor.
In cases where the internal queue is full (either because the Host queue is full or there was not enough PCI
bandwidth) and new descriptors are generated, the new descriptors are discarded. CX28500 indicates it has lost
interrupts internally by overwriting the bit field ILOST in the last Interrupt Descriptor in the internal queue. The
ILOST indication represents one or more lost descriptors.
6.3.1.3.3
The Host must monitor the INTA# signal line at all times. An assertion of this line signifies the updating of the
WRPTR field in the Interrupt Status Descriptor, indicating that Interrupt Descriptors have been transferred to the
Interrupt Queue in shared memory from the internal interrupt queue.
Upon detection of the INTA# assertion, the Host must perform a direct read of the Interrupt Status Descriptor from
within CX28500. This descriptor provides the offset to the location of the first descriptor in the Host queue that has
not been served, the offset to the location of the last descriptor serviced by the Host, and the determination if the
queue is full. The INTA* signal is deasserted on each read of the Interrupt Status Descriptor.
The Host applies its interrupt service routines to service each of the descriptors. As the Host finishes servicing a
number of descriptors, it must write the offset to the location of the last serviced descriptor back into the RDPTR
field of the Interrupt Status Descriptor. A write to this field indicates to CX28500 that the descriptor locations, which
were waiting to be serviced, have been serviced and new descriptors can be written.
Figure 6-1
28500-DSH-002-C
illustrates the operation of INTA*.
NOTE:
INTA# Signal Line
CX28500 continues to write to available space regardless of whether the Host updates the
RDPTR field. The difference between the two interrupt queue pointers RDPTR and WRPTR
indicates the number of interrupts still need to be serviced. When calculating the number of
outstanding interrupts, please make sure to take care of offsets, or pointers, wraparound.
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