cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 170

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

10.2.3
The EBUS timing is derived directly from the PCI clock (PCLK) input into CX28500.
The EBUS clock can have the same frequency as the PCI clock, or it can have half the frequency of the PCI clock.
This option is configured in the EBUS Configuration register. Please see
Table 10-9.
Figure 10-4. EBUS Reset Timing
Table 10-10. EBUS Input/Output Timing Parameters
28500-DSH-002-C
FOOTNOTE:
(1)
FOOTNOTE:
(1)
(2)
For purposes of active/float timing measurements, the hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
T
Minimum and maximum times are evaluated at 80 pF equivalent load. Actual test capacitance may vary, and results should be correlated
to these specifications.
For purposes of active/float timing measurements, the hi-Z or off state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification at 80 pF equivalent load.
Symbol
Symbol
val
T
GENERAL NOTE:
rst_off
T
T
T
T
T
val
off
(ptp)
on
ds
dh
EBUS Reset Parameters
ECLK to Signal Valid Delay—Bused Signal
ECLK to Signal Valid Delay—Point To Point
Float to Active Delay
Active to Float Delay
Input Setup Time to Clock – Bused Signal
Input Hold Time from Clock
Active to Inactive Delay
Expansion Bus (EBUS) Timing and Switching Characteristics
The EBUS reset is dependent on the PRST* (PCI Reset) signal being asserted low.
Three-state
Output
Reset
EBUS
EBUS
Input
(2)
(2)
PCI
Parameter
(1)
Parameter
Mindspeed Proprietary and Confidential
Mindspeed Technologies
(
1)
(1)
T
rst_off
Min
—
®
Electrical and Mechanical Specification
Input Ignored
Min
Reset Period
–4
–5
—
18
2
0
Three-state
Table 6-12
Max
for more detail.
28
Max
12
—
20
—
—
6
Units
Units
ns
500052_062
ns
ns
ns
ns
ns
ns
155