cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 94

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

6.2.2
The Receive and Transmit Port Alive registers are read-only registers. These registers can only be accessed via
direct PCI read.
Each bit of the Receive and Transmit Port Alive register represents the device port number. Refer to
and
Table 6-12.
Table 6-13.
These registers operate as a gate which enables or disables the access to the Port Configuration register. If the
corresponding bit of the Receive and Transmit Port Alive register is set, a new port configuration for the specified
port is allowed.
After a PCI reset or Software Chip reset, all 32 bits of the Receive and Transmit Port Alive register are cleared (set
to 0). Each bit is automatically set to 1 after 8 or 16 serial clock cycle occur on that specific port. After the
corresponding bit is set to 1, the Host can write to the Port Configuration register. In addition, Port Alive can also be
reset by writing to the Port Configuration register. If the Host writes to a dead port, the SRQ completes but the
register is not modified.
The Host cannot program a new port configuration until the corresponding bit/port is set to 1 in the Port Alive
register depending upon the direction of receive or transmit.
A proper configuration sequence for accessing the Port Configuration register is as follows:
1. Host polls the Port Alive register for the specific port/direction and waits (at an interval of 8–16 line clocks) until
2. Host issues a Service Request (SRQ) Port Configuration command and waits for a Service Request
3. Host gets the SACK.
4. Host checks if a new port configuration is allowed by checking he corresponding bit in the Port Alive register.
28500-DSH-002-C
the corresponding bit in the Port Alive register is set.
Acknowledge (SACK), or polls the SR length to determine when the table entry is completed.
Go to 1.
6-13
31:0
31:0
Bit
Bit
for these registers.
Receive Port Alive Register
Transmit Port Alive Register
NOTE:
Field Name
Field Name
RPA [31:0]
Port Alive Registers
TPA [31:0]
Writing to the Port Configuration register causes the corresponding bit from the Port Alive
register to be cleared. This bit is automatically set to 1 after 8 or 16 serial clocks occur;
therefore a new port configuration is allowed.
Value
Value
0
0
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Mindspeed Technologies
Type
Type
RO
RO
This register controls the access to the Receive Port Configuration
register. If one of 32 bits is set to 1, then the Receive Port
Configuration for that specific port is allowed.
This register controls the access to the Transmit Port Configuration
register. If one of 32 bits is set to 1, then the Transmit Port
Configuration for that specific port is allowed.
®
Description
Description
Memory Organization
Tables 6-12
79