cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 197

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure B-1
back-to-back feature enabled. CX28500 performs as a master while operating at 64-bit address-data, a burst write
of 4 dwords, which are transferred during the first cycle and a burst write of 6 dwords which are transferred during
the second cycle. It is seen that both transaction cycles require 4 PCLK cycles.
Figure B-1.
28500-DSH-002-C
GENERAL NOTE:
1. BEx means Byte Enable, where x is a numerical value between 1 and 8. For example, BE1 means byte one is enabled.
C/BE#[3:0]
C/BE#[7:4]
DEVSEL#
AD[63:32]
FRAME#
illustrates, in a specific scenario, CX28500’s PCI transactions while operating as a master and fast
AD[31:0]
REQ64#
ACK64#
PAR64
TRDY#
IRDY#
PAR
CLK
PCI Burst Write: Two 64-bit Fast Back-to-Back Transactions to Same Target
Appendix B: Example of an Arbitration
Bus Cmd
Address
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Mindspeed Technologies
Data1
Data2
BE1
BE2
Data3
Data4
BE3
BE4
for Fast Back-to-Back and
Non-Fast Back-to-Back
Transactions
Bus Cmd
Address
®
Data1
Data2
BE1
BE2
Data3
Data4
BE3
BE4
Data5
Data6
BE5
BE6
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