cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 87

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-2.
It is critically important that upon channel activation, shared memory and internal registers must be initialized, valid,
and available to CX28500. CX28500 uses the information within the shared memory descriptors to transfer data
between the serial interface and shared memory. CX28500 assumes the information is valid once a channel is
activated.
6.2
6.2.1
The registers that need to be configured and checked to enable the activity of the service request mechanism are
as follows:
•
•
28500-DSH-002-C
RSIU Time Slot Pointer
RSIU Port Configuration
RSLP Max Message Length1
RSLP Max Message Length2
RSLP Max Message Length3
Receive Base Address Head Pointer (RBAHP)
Transmit Base Address Head Pointer (TBAHP)
EBUS Configuration
Global Configuration
TSLP Channel Status
TSLP Channel Configuration
TDMA Buffer Allocation
TDMA Configuration
TSIU Time Slot Configuration
TSIU Time Slot Pointer
TSIU Port Configuration
GENERAL NOTE:
1. These registers must be accessed through the Service Request Mechanism. As shown in
2. For better performance and ease of implementation, it is recommended that this Service Request memory block be separated into two
addresses are written into bits [18:0] at the Indirect Register Map Address field, which is located in the Device Configuration Descriptor.
blocks for access. Service Request Block 1 starts at address 00000h and ends at address 0811Ch. Service Request Block 2 starts at
address 10000h and ends at address 18100h. This separation is made possible by the unused memory gap occurring between the Global
Configuration register and the TSLP Channel Status registers.
Service Request Length register (see
Service Request Pointer register (see
Indirect Register Map Address Accessible via Service Request Mechanism (2 of 2)
Register
Global Registers
Service Request Mechanism
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Mindspeed Technologies
Table
Table
Address
08000h
08080h
08100h
08104h
08108h
0810Ch
08110h
08114h
08118h
10000h
11000h
12000h
13000h
14000h
18000h
18080h
6-3)
6-4)
Number of
Registers
dword
1024
1024
1024
1024
4096
32
32
32
32
1
1
1
1
1
1
1
®
Per Time Slot
Number of
Per Channel
Per Channel
Per Channel
Per Channel
instances
Per Port
Per Port
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Per Chip
Per Port
Per Port
Table
6-7, these registers’ corresponding
Reset Value
Memory Organization
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Access
Type
72