cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 118

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 6-33.
6.7.5
6.7.5.1
The transmit time slot map consists of 4096 time slot descriptors. The entire transmit map contains configuration
information for 4096 separate time slots. The CX28500’s serial ports support 4096 time slots, which can be
configured among the CX28500’s 32 transmit serial ports by setting the TSIU Time Slot Pointer Assignment.
Numerous mappings of time slots are possible, and multiple time slots can be mapped to a single channel;
however each time slot can map to only one channel at a time. For each serial port, two time slot maps are
required: one for transmit functions and one for receive functions. The two separate maps are configured
independently for transmit direction (TSIU Time Slot Configuration Descriptor and TSIU Time Slot Pointer
Assignment) and receive direction (RSIU Time Slot Configuration Descriptor and RSIU Time Slot Pointer
Assignment). These pointers are described in
Table 6-35
6.7.5.2
There is an TSIU Time Slot Configuration Descriptor for each time slot (refer to
There are 4096 entries in memory that set the translation between time slots and logical channels for each of
CX28500's 32 ports. The actual mapping of these time slot descriptors to the 32 ports is done by 32 sets of pointer
pairs (receive and transmit), one pair set for each port, which indicates the start and the end address of the
28500-DSH-002-C
15
14
13
12:0
FOOTNOTE:
(1)
Bit
The normal mode of operation of the CX28500 is to overwrite the Tx Buffer Descriptor with Tx Buffer Status Descriptor. This bit is used
to inhibit this behavior, so that when it is set, the Tx Buffer Descriptor is not overwritten and the Host must rely on interrupts to find out
when the CX28500 relinquishes ownership of the buffers.
specifies the content of each entry.
TDMA_TRSHOLD[12:0]
TDMA Channel Configuration Register (2 of 2)
AUTOENABLE
Field Name
INHTBSD
ONRIEN
TSIU Time Slot Configuration Register
Time Slot Map
TSIU Time Slot Configuration Descriptor
(1)
Value
Mindspeed Proprietary and Confidential
—
Mindspeed Technologies
0
1
0
1
0
1
Inhibit Transmit Buffer Status Descriptor disabled. At the end of each Transmit Data Buffer,
overwrite Tx Buffer Descriptor with Tx Buffer Status Descriptor.
Inhibit Transmit Buffer Status Descriptor enabled. At the end of each Transmit Data Buffer, do
not overwrite Tx Buffer Descriptor with Tx Buffer Status Descriptor.
ONR Interrupt disabled.
ONR Interrupt enabled. Interrupt generated when a new buffer descriptor is read from the
Host memory, the ownership bit state is owned by the Host, and the NP bit field is 1, and the
DMA is in mid-message.
Automatic fetch feature disabled.
Automatic fetch feature enabled. Attempts fetching of more Shared memory as soon as it
has 32 free dwords in the channel buffer.
Threshold value. The value programmed into this field must not exceed the channel’s buffer
size. The threshold value indicates the following:
1.
2.
Table
When the buffer contains less data than the threshold, a request to the TDMA to
serve this channel is generated. An attempt to read more data from the Host
memory is made.
When a transmission of a new message can start. When the buffer contains less
data than the threshold, no new transmission starts unless there is a whole
message already in the internal FIFO.
6-34.
®
Description
Table
6-34).
Memory Organization
103