MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 139

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

9.4.1 External Pin Reset
9.4.2 Active Resets from Internal Sources
MC68HC908AS60 — Rev. 1.0
MOTOROLA
CGMOUT
RST
IAB
PC
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See
Figure 9-4
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See
Figure
opcode, COP timeout, LVI, or POR. See
or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 9-4. External Reset Timing
9-5. An internal reset can be caused by an illegal address, illegal
System Integration Module (SIM)
Reset Type
All others
shows the relative timing.
POR/LVI
Go to: www.freescale.com
Table 9-2. PIN Bit Set Timing
Number of Cycles Required to Set PIN
VECT H
4163 (4096 + 64 + 3)
VECT L
Figure 9-6
67 (64 + 3)
System Integration Module (SIM)
Table 9-2
Reset and System Initialization
. Note that for LVI
for details.
Technical Data
Figure
9-5.
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