MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 252

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

Serial Communications Interface (SCI)
Technical Data
252
Software latency may allow an overrun to occur between reads of SCS1
and SCDR in the flag-clearing sequence.
normal flag-clearing sequence and an example of an overrun caused by
a delayed flag-clearing sequence. The delayed read of SCDR does not
clear the OR bit because OR was not set when SCS1 was read. Byte 2
caused the overrun and is lost. The next flag-clearing sequence reads
byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-clearing
routine can check the OR bit in a second read of SCS1 after reading the
data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the
RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in
SCC3 is also set. Clear the NF bit by reading SCS1 and then reading
the SCDR. Reset clears the NF bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Noise detected
0 = No noise detected
BYTE 1
BYTE 1
Serial Communications Interface (SCI)
Go to: www.freescale.com
READ SCS1
READ SCDR
Figure 17-13. Flag Clearing Sequence
SCRF = 1
BYTE 1
OR = 0
READ SCDR
READ SCS1
DELAYED FLAG CLEARING SEQUENCE
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
BYTE 2
SCRF = 1
BYTE 1
OR = 0
READ SCDR
READ SCS1
SCRF = 1
BYTE 2
OR = 0
Figure 17-13
BYTE 3
BYTE 3
MC68HC908AS60 — Rev. 1.0
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
shows the
BYTE 4
BYTE 4
MOTOROLA