MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 315

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AS60 — Rev. 1.0
MOTOROLA
NOTE:
NOTE:
MISO — Master In/Slave Out Bit
SS — Slave Select Bit
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
TACH[1:0] — Timer Channel I/O Bits
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIMA. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. (See
RxD — SCI Receive Data Input Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. (See
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and
MODFEN bit is low, the PTE4/SS pin is available for general-purpose
I/O. (See
slave, the DDRF4 bit in data direction register E (DDRE) has no effect
on the PTE4/SS pin.
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB–ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. (See
22.9.4 TIMA Channel Status and Control
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. (See
SCI Control Register
Freescale Semiconductor, Inc.
For More Information On This Product,
18.14.1 SPI Control
18.13.4 SS (Slave
Go to: www.freescale.com
Input/Output (I/O) Ports
1.)
Select).) When the SPI is enabled as a
Register.)
Table
Table
20-5.)
20-5.)
Registers.)
Input/Output (I/O) Ports
Technical Data
17.9.1
Port E
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