MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 253

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

17.9.5 SCI Status Register 2
MC68HC908AS60 — Rev. 1.0
MOTOROLA
Address:
FE — Receiver Framing Error Bit
PE — Receiver Parity Error Bit
SCI status register 2 contains flags to signal these conditions:
BKF — Break Flag Bit
Reset:
Read:
Write:
This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
•
•
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request. Clear BKF by
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Framing error detected
0 = No framing error detected
1 = Parity error detected
0 = No parity error detected
Break character detected
Incoming data
Serial Communications Interface (SCI)
$0017
Bit 7
0
Figure 17-14. SCI Status Register 2 (SCS2)
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= Unimplemented
6
0
5
0
4
0
Serial Communications Interface (SCI)
3
0
2
0
BKF
1
0
Technical Data
I/O Registers
Bit 0
RPF
0
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