MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 357

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

21.7 BDLC CPU Interface
MC68HC908AS60 — Rev. 1.0
MOTOROLA
The CPU interface provides the interface between the CPU and the
BDLC and consists of these five user registers:
1. BDLC analog and roundtrip delay register (BARD)
2. BDLC control register 1 (BCR1)
3. BDLC control register 2 (BCR2)
4. BDLC state vector register (BSVR)
5. BDLC data register (BDR)
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller-Digital (BDLC-D)
Go to: www.freescale.com
Figure 21-15. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
CPU INTERFACE
MUX INTERFACE
TO J1850 BUS
TO CPU
Byte Data Link Controller-Digital (BDLC-D)
BDLC
BDLC CPU Interface
Technical Data
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