MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 186

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MC68HC908AS60MFN

Manufacturer Part Number
MC68HC908AS60MFN
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Break Module
12.4 Functional Description
Technical Data
186
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).
These two events can cause a break interrupt to occur:
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
IAB[15:0]
A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
Software writes a logic 1 to the BRKA bit in the break status and
control register.
Figure 12-1
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Figure 12-1. Break Module Block Diagram
IAB[15:8]
IAB[7:0]
Break Module
BREAK ADDRESS REGISTER HIGH
BREAK ADDRESS REGISTER LOW
shows the structure of the break module.
8-BIT COMPARATOR
8-BIT COMPARATOR
MC68HC908AS60 — Rev. 1.0
CONTROL
MOTOROLA
BREAK

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