MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 169

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

10.6 CGM Registers
10.6.1 PLL Control Register
MC68HC908AS60 — Rev. 1.0
MOTOROLA
Address:
Three registers control and monitor operation of the CGM:
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, and the base clock selector bit.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Flag Bit
Reset:
Read:
Write:
1. PLL control register (PCTL)
2. PLL bandwidth control register (PBWC)
3. PLL programming register (PPG)
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates a CPU interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
1 = Change in lock condition
0 = No change in lock condition
$001C
PLLIE
Bit 7
0
Clock Generator Module (CGM)
Go to: www.freescale.com
Figure 10-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
BCS
4
0
3
1
1
Clock Generator Module (CGM)
2
1
1
CGM Registers
1
1
1
Technical Data
Bit 0
1
1
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