MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 210
MC68HC908AS60MFN
Manufacturer Part Number
MC68HC908AS60MFN
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AS60MFN.pdf
(454 pages)
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Low-Voltage Inhibit (LVI) Module
15.3 Features
15.4 Functional Description
Technical Data
210
Features of the LVI module include:
Figure 15-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
below that level for nine or more consecutive CPU cycles. LVISTOP
enables the LVI module during stop mode. This will ensure when the
STOP instruction is implemented, and the LVI will continue to monitor
the voltage level on V
configuration register (CONFIG-1). See
Register
•
•
•
Freescale Semiconductor, Inc.
DETECTOR
LOW V
For More Information On This Product,
Programmable LVI reset
Programmable power consumption
Digital filtering of V
V
DD
DD
(CONFIG-1).
Low-Voltage Inhibit (LVI) Module
Go to: www.freescale.com
shows the structure of the LVI module. The LVI is enabled
V
V
DD
DD
Figure 15-1. LVI Module Block Diagram
DD
> LVI
< LVI
falls below a voltage, LVI
CPU CLOCK
TRIP
TRIP
= 0
= 1
ANLGTRIP
DD
FROM CONFIG-1
. LVIPWR, LVISTOP, and LVIRST are in the
LVIPWR
DD
pin level
DIGITAL FILTER
FROM CONFIG-1
STOP MODE
BYPASS
LVISTOP
FILTER
V
DD
Section 11. Configuration
LVIOUT
TRIPF
FROM CONFIG-1
MC68HC908AS60 — Rev. 1.0
LVIRST
, and remains at or
MOTOROLA
LVI
RESET
DD
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