MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 219

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

16.5 IRQ Pin
MC68HC908AS60 — Rev. 1.0
MOTOROLA
NOTE:
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ1
latch. A vector fetch, software clear, or reset clears the IRQ1 latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ1 latch:
The vector fetch or software clear and the return of the IRQ pin to logic 1
can occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ1 latch.
The IRQF1 bit in ISCR can be used to check for pending interrupts. The
IRQF1 bit is not affected by the IMASK1 bit, which makes it useful in
applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ1 latch. Writing to the ACK1 bit
can also prevent spurious interrupts due to noise. Setting ACK1
does not affect subsequent transitions on the IRQ pin. A falling
edge on IRQ that occurs after writing to the ACK1 bit latches
another interrupt request. If the IRQ1 mask bit, IMASK1, is clear,
the CPU loads the program counter with the vector address at
locations $FFFA and $FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, the IRQ1 latch remains set.
External Interrupt Module (IRQ)
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External Interrupt Module (IRQ)
Technical Data
IRQ Pin
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