MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 183

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908AS60 — Rev. 1.0
MOTOROLA
WARNING:
NOTE:
SSREC — Short Stop Recovery Bit
If using an external crystal oscillator, do not set the SSREC bit.
COPL — COP Long Timeout Bit
STOP — STOP Instruction Enable Bit
COPD — COP Disable Bit
Extra care should be exercised when using this emulation part for
development of code to be run in ROM-based M68HC08AS Family
parts that the options selected by setting the CONFIG-1 register
match exactly the options selected on any ROM code request
submitted. The enable/disable logic is not necessarily identical in
all parts of the AS Family. If there is any doubt, check with a local
field applications representative.
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. See
9.7.2 Stop
COPL enables the shorter COP timeout period. See
Computer Operating Properly (COP)
STOP enables the STOP instruction.
COPD disables the COP module. See
Operating Properly (COP)
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
1 = COP timeout period is 8,176 CGMXCLK cycles.
0 = COP timeout period is 262,128 CGMXCLK cycles.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
1 = COP module disabled
0 = COP module enabled
Configuration Register (CONFIG-1)
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Mode.
Module.
Section 14. Computer
Configuration Register (CONFIG-1)
Module.
Functional Description
Section 14.
Technical Data
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