MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 161

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

10.4.2.2 Acquisition and Tracking Modes
10.4.2.3 Manual and Automatic PLL Bandwidth Modes
MC68HC908AS60 — Rev. 1.0
MOTOROLA
The PLL filter is manually or automatically configurable into one of two
operating modes:
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See
interrupt requests are enabled, the software can wait for a PLL CPU
interrupt request and then check the LOCK bit. If CPU interrupts are
disabled, software can poll the LOCK bit continuously (during PLL
startup, usually) or at periodic intervals. In either case, when the LOCK
bit is set, the VCO clock is safe to use as the source for the base clock.
See
source for the base clock and the LOCK bit is clear, the PLL has suffered
a severe noise hit and the software must take appropriate action,
depending on the application. See
1. Acquisition mode — In acquisition mode, the filter can make large
2. Tracking mode — In tracking mode, the filter makes only small
Freescale Semiconductor, Inc.
10.4.3 Base Clock Selector
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frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. See
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. See
automatically in tracking mode when it’s not in acquisition mode or
when the ACQ bit is set.
Clock Generator Module (CGM)
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10.6.2 PLL Bandwidth Control
10.4.3 Base Clock Selector
10.6.2 PLL Bandwidth Control
Circuit. If the VCO is selected as the
10.7
Interrupts.
Clock Generator Module (CGM)
Circuit. The PLL is
Register. If PLL CPU
Register.
Functional Description
Technical Data
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