MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 309

• Manufacturer Part Number: MC68HC908AS60MFN
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

20.5.2 Data Direction Register C
MC68HC908AS60 — Rev. 1.0
MOTOROLA
Address:
PTC[5:0] — Port C Data Bits
MCLK — T12 System Clock Bit
Data direction register C (DDRC) determines whether each port C pin is
an input or an output. Writing a logic 1 to a DDRC bit enables the output
buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
MCLKEN — MCLK Enable Bit
DDRC[5:0] — Data Direction Register C Bits
Reset:
Read:
Write:
These read/write bits are software-programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
The system clock is driven out of PTC2 when enabled by MCLKEN bit
in PTCDDR7.
This read/write bit enables MCLK to be an output signal on PTC2. If
MCLK is enabled, PTC2 is under the control of MCLKEN. Reset
clears this bit.
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = MCLK output enabled
0 = MCLK output disabled
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
MCLKEN
$0006
Bit 7
R
0
Figure 20-9. Data Direction Register C (DDRC)
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Input/Output (I/O) Ports
= Reserved
R
6
0
0
DDRC5
5
0
DDRC4
4
0
DDRC3
3
0
DDRC2
2
0
Input/Output (I/O) Ports
DDRC1
1
0
Technical Data
DDRC0
Bit 0
Port C
0
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