MC68HC908AS60MFN MOTOROLA [Motorola, Inc], MC68HC908AS60MFN Datasheet - Page 369
MC68HC908AS60MFN
Manufacturer Part Number
MC68HC908AS60MFN
Description
HCMOS Microcontroller Unit
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908AS60MFN.pdf
(454 pages)
- Current page: 369 of 454
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MC68HC908AS60 — Rev. 1.0
MOTOROLA
NOTE:
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
onto the J1850 bus from a corrupted message.
If the TMIFR0 bit is set, the BDLC will attempt to transmit the
normalization symbol followed by the byte in the BDR. After the byte
in the BDR has been loaded into the transmit shift register, a TDRE
interrupt (see
to the main message transmit sequence. The programmer should
then load the next byte of the IFR into the BDR for transmission.
When the last byte of the IFR has been loaded into the BDR, the
programmer should set the TEOD bit in the BCR2. This will instruct
the BDLC to transmit an EOD symbol once the byte in the BDR is
transmitted, indicating the end of the IFR portion of the message
frame. The BDLC will not append a CRC when the TMIFR0 is set.
If the programmer attempts to set the TMIFR0 bit after the EOD
symbol has been received from the bus, the TMIFR0 bit will remain in
the reset state, and no attempt will be made to transmit an IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared, and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional 1 bits (active short bits) will be sent out.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = The TMIFR0 bit will be cleared automatically, once the BDLC
Byte Data Link Controller-Digital (BDLC-D)
has successfully transmitted the EOD symbol, by the detection
of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to
the BDR after the TDRE interrupt.
Go to: www.freescale.com
21.7.4 BDLC State Vector
Byte Data Link Controller-Digital (BDLC-D)
Register) will occur similar
BDLC CPU Interface
Technical Data
369
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