MA180023 Microchip Technology, MA180023 Datasheet - Page 309

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5.9
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the BRG is loaded with the contents of
SSPxADD<5:0> and begins counting. The SDAx pin is
released (brought high) for one BRG count (T
When the BRG times out, and if SDAx is sampled high,
the SCLx pin will be deasserted (brought high). When
SCLx is sampled high, the BRG is reloaded with the
contents of SSPxADD<6:0> and begins counting.
SDAx and SCLx must be sampled high for one T
This action is then followed by assertion of the SDAx
pin (SDAx = 0) for one T
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the BRG will not be
reloaded, leaving the SDAx pin held low. As soon as a
Start condition is detected on the SDAx and SCLx pins,
the Start bit (SSPxSTAT<3>) will be set. The SSPxIF bit
will not be set until the BRG has timed out.
FIGURE 18-22:
© 2009 Microchip Technology Inc.
Write to SSPxCON2
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
REPEATED START CONDITION WAVEFORM
SDAx
SCLx
BRG
occurs here:
end of XMIT
while SCLx is high.
SDAx = 1,
SCLx (no change).
2
C logic
BRG
BRG
).
.
T
SDAx = 1,
SCLx = 1
BRG
PIC18F46J11 FAMILY
Immediately following the SSPxIF bit getting set, the
user may write the SSPxBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional 8 bits
of address (10-bit mode) or 8 bits of data (7-bit mode).
18.5.9.1
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
T
BRG
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
2: A bus collision during the Repeated Start
BRG
Because queueing of events is not
allowed, writing of the lower five bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDAx is sampled low when SCLx
• SCLx goes low before SDAx is
At completion of Start bit,
hardware clears RSEN bit
WCOL Status Flag
S bit set by hardware
goes from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
and sets SSPxIF
Write to SSPxBUF occurs here
T
BRG
1st bit
T
BRG
DS39932C-page 309