MA180023 Microchip Technology, MA180023 Datasheet - Page 52

• Manufacturer Part Number: MA180023
• Description: MODULE PLUG-IN PIC18F46J11 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA180023

• Accessory Type: Plug-In Module (PIM) - PIC18F46J11
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: PIC18
• Supported Devices: Stand-alone Or W/ HPC(DM183022) Or PIC18(DM183032)
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18FxxJxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: HPC Explorer Board (DM183022) or PIC18 Explorer Board (DM183032)
• For Use With: DM183032 - BOARD EXPLORER PICDEM PIC18DM183022 - BOARD DEMO PIC18FXX22 64/80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F46J11 FAMILY
3.6.9
Deep
Register 3-1 through Register 3-6.
REGISTER 3-1:
REGISTER 3-2:
DS39932C-page 52
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2
bit 1
bit 0
Note 1:
DSEN
R/W-0
U-0
—
Sleep
(1)
In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN.
This is the value when V
DEEP SLEEP MODE REGISTERS
mode
DSEN: Deep Sleep Enable bit
1 = Deep Sleep mode is entered on a SLEEP command
0 = Sleep mode is entered on a SLEEP command
Unimplemented: Read as ‘0’
(Reserved): Always write ‘0’ to this bit
DSULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = ULPWU module is enabled in Deep Sleep
0 = ULPWU module is disabled in Deep Sleep
RTCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled
Unimplemented: Read as ‘0’
ULPWDIS: Ultra Low-Power Wake-up Disable bit
1 = ULPWU wake-up source is disabled
0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1)
DSBOR: Deep Sleep BOR Event Status bit
1 = DSBOREN was enabled and V
0 = DSBOREN was disabled or V
RELEASE: I/O Pin State Release bit
Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will
release the I/O pins and allow their respective TRIS and LAT bits to control their states.
but did not fall below V
U-0
U-0
—
—
DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh)
DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch)
registers
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
are
U-0
U-0
DD
—
—
is initially applied.
provided
DSBOR
(1)
DD
U-0
U-0
—
—
DD
in
did not drop below the DSBOR arming voltage during Deep Sleep
dropped below the DSBOR arming voltage during Deep Sleep,
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
(Reserved)
ULPWDIS
R/W-0
R/W-0
© 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
DSULPEN
R/W-0
DSBOR
R/W-0
(1)
RTCWDIS
RELEASE
R/W-0
R/W-0
(1)
bit 0
bit 0